PDP-6 prehistory

Account from Peter Samson

Back in 1960, the MIT Computation Center was starting to consider its future needs, and one part of this was to evaluate as many existing computer systems as possible. Prof. Teager tasked me with writing a few algorithms (polynomial evaluation, vector processing, etc.) in assembly language for as many machines as I could find documentation about, primarily to determine how fast the machines were. This was a great education. One computer, for instance, had a three-bit index field, as did the IBM mainframes of the time, but it selected from among 7 index registers. (The IBM 36-bit systems at that time had only 3 index registers, each denoted by one bit in the index field.) Well, that was neat. Then rummaging through file drawers I found an RFQ that IBM had proposed to a customer for a special feature on an IBM 650: By a mode change instruction, the 650 could change from using its accumulator to a second "auxiliary" accumulator. From the tedious programming of machines with only one accumulator I saw how having a second one would be very useful. All this percolated in my mind for several years.

Then, I think in 1963, my friend Alan Kotok, who was then working at DEC as part of his MS degree, mentioned that DEC was contemplating making a larger computer than the 18-bit machines it was then selling. I don't think it was initially planned to be as large as 36 bits; I don't remember the specific word size but your reference to 24 bits certainly fits. So, melding the 3-bit field to select among 7 index registers, and the idea of multiple accumulators, I proposed one set of registers serving both functions, addressable separately for each purpose in every instruction. At that time I proposed 8 such registers. The advantages were obvious: multiple accumulators to hold several running values; accumulators as index registers to calculate complex indexes (e.g. for multidimensional arrays); and only one arithmetic unit rather than separate "A Boxes" and "B Boxes" to use the old British terminology. I described this idea to Alan over dinner at Al Trager's restaurant in Brookline. Alan took it to DEC, and the word size eventually grew to 36 bits, with room for 4-bit accumulator and index fields, and the 16 fast registers that we know and love.

Another part of the idea that I described to Alan was a separate class of instructions, that instead of a main memory address had multiple accumulator addresses to be interpreted sequentially. Two such instructions that I remember were (a) polynomial evaluation: multiply A by X, add B, multiply by X, add C, multiply by X, etc., and add (or store) the result into S; (b) difference engine: add A into B, add the result into C, etc. This proposal went nowhere.

Here's one more item of trivia that I happen to recall about the PDP-6 development. The byte instructions LDB, DPB, etc. (I don't know whose idea they were) had the option to increment the pointer after the data-byte reference: LDBI, DPBI. Development was well along and I was writing a compiler for the not-yet-existent machine when Gordon Bell phoned me at home (no doubt he spoke with all the programmers) and asked if it would be a hardship if the increment occurred first instead of last. He had realized that post-increment would require a lot more hardware, especially with interrupts possible between memory references. I said it was less attractive but I could live with it. So we have ILDB and IDPB instead of LDBI and DPBI.